High performance system-on-chip using post passivation process

ABSTRACT

The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface.

This application is a continuation of application Ser. No. 11/092,379,filed on Mar. 29, 2005, now pending, which is a continuation ofapplication Ser. No. 10/303,451, Nov. 25, 2002, now issued as U.S. Pat.No. 6,897,507, which is a Continuation of application Ser. No.10/156,590, May 28, 2002, now issued as U.S. Pat. No. 6,489,647, whichis a Divisional Application of application Ser. No. 09/970,005, Oct. 3,2001, now issued as U.S. Pat. No. 6,455,885, which is a DivisionalApplication of application Ser. No. 09/721,722, Nov. 27, 2000, nowissued as U.S. Pat. No. 6,303,423 which is a continuation-in-part ofapplication Ser. No. 09/637,926, Aug. 14, 2000, now abandoned, which isa continuation-in-part of application Ser. No. 09/251,183, Feb. 17,1999, now issued as U.S. Pat. No. 6,383,916, which is acontinuation-in-part of application Ser. No. 09/216,791, Dec. 21, 1998,now abandoned.

TECHNICAL FIELD

The invention relates to the manufacturing of high performanceIntegrated Circuit (IC's), and, more specifically, to methods ofcreating high performance electrical components (such as an inductor) onthe surface of a semiconductor substrate by reducing the electromagneticlosses that are typically incurred in the surface of the substrate.

BACKGROUND ART

The continued emphasis in the semiconductor technology is to createimproved performance semiconductor devices at competitive prices. Thisemphasis over the years has resulted in extreme miniaturization ofsemiconductor devices, made possible by continued advances ofsemiconductor processes and materials in combination with new andsophisticated device designs. Most of the semiconductor devices that areat this time being created are aimed at processing digital data. Thereare however also numerous semiconductor designs that are aimed atincorporating analog functions into devices that simultaneously processdigital and analog data, or devices that can be used for the processingof only analog data. One of the major challenges in the creation ofanalog processing circuitry (using digital processing procedures andequipment) is that a number of the components that are used for analogcircuitry are large in size and are therefore not readily integratedinto devices that typically have feature sizes that approach thesub-micron range. The main components that offer a challenge in thisrespect are capacitors and inductors, since both these components are,for typical analog processing circuits, of considerable size.

A typical application for inductors of the invention is in the field ofmodern mobile communication applications that make use of compact,high-frequency equipment. Continued improvements in the performancecharacteristics of this equipment has over the years been achieved,further improvements will place continued emphasis on lowering the powerconsumption of the equipment, on reducing the size of the equipment, onincreasing the operational frequency of the applications and on creatinglow noise levels. One of the main applications of semiconductor devicesin the field of mobile communication is the creation of Radio Frequency(RF) amplifiers. RF amplifiers contain a number of standard components,a major component of a typical RF amplifier is a tuned circuit thatcontains inductive and capacitive components. Tuned circuits form,dependent on and determined by the values of their inductive andcapacitive components, an impedance that is frequency dependent,enabling the tuned circuit to either present a high or a low impedancefor signals of a certain frequency. The tuned circuit can thereforeeither reject or pass and further amplify components of an analogsignal, based on the frequency of that component. The tuned circuit canin this manner be used as a filter to filter out or remove signals ofcertain frequencies or to remove noise from a circuit configuration thatis aimed at processing analog signals. The tuned circuit can also beused to form a high electrical impedance by using the LC resonance ofthe circuit and to thereby counteract the effects of parasiticcapacitances that are part of a circuit. One of the problems that isencountered when creating an inductor on the surface of a semiconductorsubstrate is that the self-resonance that is caused by the parasiticcapacitance between the (spiral) inductor and the underlying substratewill limit the use of the inductor at high frequencies. As part of thedesign of such an inductor it is therefore of importance to reduce thecapacitive coupling between the created inductor and the underlyingsubstrate.

At high frequencies, the electromagnetic field that is generated by theinductor induces eddy currents in the underlying silicon substrate.Since the silicon substrate is a resistive conductor, the eddy currentswill consume electromagnetic energy resulting in significant energyloss, resulting in a low Q capacitor. This is the main reason for a lowQ value of a capacitor, whereby the resonant frequency of 1/√(LC) limitsthe upper boundary of the frequency. In addition, the eddy currents thatare induced by the inductor will interfere with the performance ofcircuitry that is in close physical proximity to the capacitor.

It has already been pointed out that one of the key components that areused in creating high frequency analog semiconductor devices is theinductor that forms part of an LC resonance circuit. In view of the highdevice density that is typically encountered in semiconductor devicesand the therefrom following intense use of the substrate surface area,the creation of the inductor must incorporate the minimization of thesurface area that is required for the inductor, while at the same timemaintaining a high Q value for the inductor.

Typically, inductors that are created on the surface of a substrate areof a spiral shape whereby the spiral is created in a plane that isparallel with the plane of the surface of the substrate. Conventionalmethods that are used to create the inductor on the surface of asubstrate suffer several limitations. Most high Q inductors form part ofa hybrid device configuration or of Monolithic Microwave IntegratedCircuits (MMIC's) or are created as discrete components, the creation ofwhich is not readily integratable into a typical process of IntegratedCircuit manufacturing. It is clear that, by combining the creation onone semiconductor monolithic substrate of circuitry that is aimed at thefunctions of analog data manipulation and analog data storage with thefunctions of digital data manipulation and digital data storage, anumber of significant advantages can be achieved. Such advantagesinclude the reduction of manufacturing costs and the reduction of powerconsumption by the combined functions. The spiral form of the inductorthat is created on the surface of a semiconductor substrate howeverresults, due to the physical size of the inductor, in parasiticcapacitances between the inductor wiring and the underlying substrateand causes electromagnetic energy losses in the underlying resistivesilicon substrate. These parasitic capacitances have a serious negativeeffect on the functionality of the created LC circuit by sharplyreducing the frequency of resonance of the tuned circuit of theapplication. More seriously, the inductor-generated electromagneticfield will induce eddy currents in the underlying resistive siliconsubstrate, causing a significant energy loss that results in low Qinductors.

The performance parameter of an inductor is typically indicated is theQuality (Q) factor of the inductor. The quality factor Q of an inductoris defined as Q=Es/El, wherein Es is the energy that is stored in thereactive portion of the component while El is the energy that is lost inthe reactive portion of the component. The higher the quality of thecomponent, the closer the resistive value of the component approacheszero while the Q factor of the component approaches infinity. Forinductors that are created overlying a silicon substrate, theelectromagnetic energy that is created by the inductor will primarily belost in the resistive silicon of the underlying substrate and in themetal lines that are created to form the inductor. The quality factorfor components differs from the quality that is associated with filtersor resonators.

For components, the quality factor serves as a measure of the purity ofthe reactance (or the susceptance) of the component, which can bedegraded due to the resistive silicon substrate, the resistance of themetal lines and dielectric losses. In an actual configuration, there arealways some physical resistors that will dissipate power, therebydecreasing the power that can be recovered. The quality factor Q isdimensionless. A Q value of greater than 100 is considered very high fordiscrete inductors that are mounted on the surface of Printed CircuitBoards. For inductors that form part of an integrated circuit, the Qvalue is typically in the range between about 3 and 10.

In creating an inductor on a monolithic substrate on which additionalsemiconductor devices are created, the parasitic capacitances that occuras part of this creation limit the upper bound of the cut-off frequencythat can be achieved for the inductor using conventional siliconprocesses. This limitation is, for many applications, not acceptable.Dependent on the frequency at which the LC circuit is designed toresonate, significantly larger values of quality factor, such as forinstance 50 or more, must be available. Prior Art has in this beenlimited to creating values of higher quality factors as separate units,and in integrating these separate units with the surrounding devicefunctions. This negates the advantages that can be obtained when usingthe monolithic construction of creating both the inductor and thesurrounding devices on one and the same semiconductor substrate. Thenon-monolithic approach also has the disadvantage that additional wiringis required to interconnect the sub-components of the assembly, therebyagain introducing additional parasitic capacitances and resistive lossesover the interconnecting wiring network. For many of the applications ofa RF amplifier, such as portable battery powered applications, powerconsumption is at a premium and must therefore be as low as possible. Byraising the power consumption, the effects of parasitic capacitances andresistive power loss can be partially compensated, but there arelimitations to even this approach. These problems take on even greaterurgency with the rapid expansion of wireless applications, such asportable telephones and the like. Wireless communication is a rapidlyexpanding market, where the integration of RF integrated circuits is oneof the most important challenges. One of the approaches is tosignificantly increase the frequency of operation to for instance therange of 10 to 100 GHz. For such high frequencies, the value of thequality factor obtained from silicon-based inductors is significantlydegraded. For applications in this frequency range, monolithic inductorshave been researched using other than silicon as the base for thecreation of the inductors. Such monolithic inductors have for instancebeen created using sapphire or GaAs as a base. These inductors haveconsiderably lower substrate losses than their silicon counterparts (noeddy current, hence no loss of electromagnetic energy) and thereforeprovide much higher Q inductors. Furthermore, they have lower parasiticcapacitance and therefore provide higher frequency operationcapabilities. Where however more complex applications are required, theneed still exists to create inductors using silicon as a substrate. Forthose applications, the approach of using a base material other thansilicon has proven to be too cumbersome while for instance GaAs as amedium for the creation of semiconductor devices is as yet a technicalchallenge that needs to be addressed. It is known that GaAs is asemiinsulating material at high frequencies, reducing theelectromagnetic losses that are incurred in the surface of the GaAssubstrate, thereby increasing the Q value of the inductor created on theGaAs surface. GaAs RF chips however are expensive, a process that canavoid the use of GaAs RF chips therefore offers the benefit of costadvantage.

A number of different approaches have been used to incorporate inductorsinto a semiconductor environment without sacrificing device performancedue to substrate losses. One of these approaches has been to selectivelyremove (by etching) the silicon underneath the inductor (using methodsof micro machining), thereby removing substrate resistive energy lossesand parasitic effects. Another method has been to use multiple layers ofmetal (such as aluminum) interconnects or of copper damasceneinterconnects.

Other approaches have used a high resistivity silicon substrate therebyreducing resistive losses in the silicon substrate. Resistive substratelosses in the surface of the underlying substrate form a dominant factorin determining the Q value of silicon inductors. Further, biased wellshave been proposed underneath a spiral conductor, this again aimed atreducing inductive losses in the surface of the substrate. A morecomplex approach has been to create an active inductive component thatsimulates the electrical properties of an inductor as it is applied inactive circuitry. This latter approach however results in high powerconsumption by the simulated inductor and in noise performance that isunacceptable for low power, high frequency applications. All of theseapproaches have as common objectives to enhance the quality (Q) value ofthe inductor and to reduce the surface area that is required for thecreation of the inductor. The most important consideration in thisrespect is the electromagnetic energy losses due to the electromagneticinduced eddy currents in the silicon substrate.

When the dimensions of Integrated Circuits are scaled down, the cost perdie is decreased while some aspects of performance are improved. Themetal connections which connect the Integrated Circuit to other circuitor system components become of relative more importance and have, withthe further miniaturization of the IC, an increasingly negative impacton circuit performance. The parasitic capacitance and resistance of themetal interconnections increase, which degrades the chip performancesignificantly. Of most concern in this respect is the voltage drop alongthe power and ground buses and the RC delay of the critical signalpaths. Attempts to reduce the resistance by using wider metal linesresult in higher capacitance of these wires.

Current techniques for building an inductor on the surface of asemiconductor substrate use fine-line techniques whereby the inductor iscreated under a layer of passivation. This however implies closephysical proximity between the created inductor and the surface of thesubstrate over which the inductor has been created (typically less than10 μm), resulting in high electro-magnetic losses in the siliconsubstrate which in turn results in reducing the Q value of the inductor.By increasing the distance between the inductor and the semiconductorsurface, the electromagnetic field in the silicon substrate will bereduced in reverse proportion to the distance, the Q value of theinductor can be increased. By therefore creating the inductor overlyingthe layer of passivation (by a post passivation process) and by, inaddition, creating the inductor on the surface of a thick layer ofdielectric (such as a polymer) that is deposited or adhered over thesurface of a layer of passivation, the Q value of the inductor can beincreased. In addition, by using wide and thick metal for the creationof the inductor, the parasitic resistance is reduced. The process of theinvention applies these principles of post passivation inductor creationwhile the inductor is created on a thick layer of dielectric using thickand wide metals.

U.S. Pat. No. 5,212,403 (Nakanishi) shows a method of forming wiringconnections both inside and outside (in a wiring substrate over thechip) for a logic circuit depending on the length of the wireconnections.

U.S. Pat. No. 5,501,006 (Gehman, Jr. et al.) shows a structure with aninsulating layer between the integrated circuit (IC) and the wiringsubstrate. A distribution lead connects the bonding pads of the IC tothe bonding pads of the substrate.

U.S. Pat. No. 5,055,907 (Jacobs) discloses an extended integrationsemiconductor structure that allows manufacturers to integrate circuitrybeyond the chip boundaries by forming a thin film multi-layer wiringdecal on the support substrate and over the chip. However, thisreference differs from the invention.

U.S. Pat. No. 5,106,461 (Volfson et al.) teaches a multi layerinterconnect structure of alternating polyimide (dielectric) and metallayers over an IC in a TAB structure.

U.S. Pat. No. 5,635,767 (Wenzel et al.) teaches a method for reducing RCdelay by a PBGA that separates multiple metal layers.

U.S. Pat. No. 5,686,764 (Fulcher) shows a flip chip substrate thatreduces RC delay by separating the power and I/O traces.

U.S. Pat. No. 6,008,102 (Alford et al.) shows a helix inductor using twometal layers connected by vias.

U.S. Pat. No. 5,372,967 (Sundaram et al.) discloses a helix inductor.

U.S. Pat. No. 5,576,680 (Ling) and U.S. Pat. No. 5,884,990 (Burghartz etal.) show other helix inductor designs.

SUMMARY OF THE INVENTION

It is the primary objective of the invention to improve the RFperformance of High Performance Integrated Circuits.

Another objective of the invention is to provide a method for thecreation of a high-Q inductor.

Another objective of the invention is to replace the GaAs chip with asilicon chip as a base on which a high-Q inductor is created.

Yet another objective of the invention is to extend the frequency rangeof the inductor that is created on the surface of a silicon substrate.

It is yet another objective of the invention to create high qualitypassive electrical components overlying the surface of a siliconsubstrate.

The above referenced continuation-in-part application adds, in a postpassivation processing sequence, a thick layer of dielectric over alayer of passivation and layers of wide and thick metal lines on top ofthe thick layer of dielectric. The present invention extends the abovereferenced continuation-in part application by in addition creating highquality electrical components, such as an inductor, a capacitor or aresistor, on a layer of passivation or on the surface of a thick layerof dielectric. In addition, the process of the invention provides amethod for mounting discrete passive electrical components at asignificant distance removed from the underlying silicon surface.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a cross section of the interconnection scheme used in theinvention.

FIG. 2 shows a cross section of an extension whereby an inductor hasbeen created on the surface of a thick layer of polyimide.

FIG. 3 shows a top view of an inductor that is created following theprocess of the invention.

FIG. 4 shows a cross section of a substrate and overlying layers, aninductor has been created on the surface of a thick layer of polyimide,a layer of ferromagnetic material has been added to further insulate theinductor from the underlying silicon substrate.

FIG. 5 a shows a cross section of a simplified version of the substrateand the layers that are created on the surface of the substrate.

FIG. 5 b shows the cross section of FIG. 5 a, an inductor has been addedabove the layer of passivation.

FIG. 6 a shows a cross section of a substrate on the surface of whichhas been deposited a layer of passivation, a capacitor has been createdon the surface of the layer of passivation.

FIG. 6 b shows a three dimensional view of an inductor that has beencreated on the surface of a layer of passivation by creating vias in athick layer of polymer.

FIG. 6 c shows a three-dimensional view of an inductor that has beencreated in a thick layer of polymer that has been deposited on thesurface of a thick layer of polyimide.

FIG. 6 d shows a top view of the layer 20 on the surface of which aninductor has been created.

FIG. 6 e shows a cross section of the structure of FIG. 6 d taken alongthe line 6 e-6 e′ of FIG. 6 d.

FIG. 6 f shows a three dimensional view of an inductor that has beencreated on the surface of a layer of passivation, the inductor has theshape of a solenoid.

FIG. 6 g shows a top view of the inductor of FIG. 6 f.

FIG. 7 shows a cross section of a substrate on the surface of which hasbeen deposited a layer of passivation over which a thick layer ofpolyimide has been deposited, a capacitor has been created on thesurface of the thick layer of polyimide.

FIG. 8 shows a cross section of a substrate on the surface of which hasbeen deposited a layer of passivation, a resistor has been created onthe surface of the layer of passivation.

FIG. 9 shows a cross section of a substrate on the surface of which hasbeen deposited a layer of passivation over which a thick layer ofpolyimide has been deposited, a resistor has been created on the surfaceof the thick layer of polyimide.

FIG. 10 shows a cross section of a silicon substrate on the surface ofwhich a discrete electrical component has been mounted, contact ballsare used whereby the distance between the substrate and the electricalcomponent is of a significant value, a thick layer of polyimide has beenused.

FIG. 11 shows a cross section of a silicon substrate on the surface ofwhich a discrete electrical component has been mounted, thick contactballs are used whereby the distance between the substrate and theelectrical component is of a significant value, no layer of polyimidehas been used.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

There is teached an Integrated Circuit structure where re-distributionand interconnect metal layers are created in layers of dielectric on thesurface of a conventional IC. A layer of passivation is deposited overthe dielectric of the re-distribution and interconnection metal layers,a thick layer of polymer is deposited over the surface of the layer ofpassivation. Under the present invention, a high-quality electricalcomponent is created on the surface of the thick layer of polymer.

The invention addresses, among others, the creation of an inductorwhereby the emphasis is on creating an inductor of high Q value on thesurface of a semiconductor substrate using methods and procedures thatare well known in the art for the creation of semiconductor devices. Thehigh quality of the inductor of the invention allows for the use of thisinductor in high frequency applications while incurring minimum loss ofpower. The invention further addresses the creation of a capacitor and aresistor on the surface of a silicon substrate whereby the mainobjective (of the process of creating a capacitor and resistor) is toreduce parasitics that are typically incurred by these components in theunderlying silicon substrate.

Referring now more specifically to FIG. 1, there is shown a crosssection of one implementation of the referenced application. The surfaceof silicon substrate 10 has been provided with transistors and otherdevices (not shown in FIG. 1). The surface of substrate 10 is covered bya dielectric layer 12, layer 12 of dielectric is therefore depositedover the devices that have been provided in the surface of the substrateand over the substrate 10. Conductive interconnect lines 11 are providedinside layer 12 that connect to the semiconductor devices that have beenprovided in the surface of substrate 10.

Layers 14 (two examples are shown) represent all of the metal layers,dielectric layers and conductive vias that are typically created on topof the dielectric layer 12, layers 14 that are shown in FIG. 1 maytherefore contain multiple layers of dielectric or insulation and thelike, conductive interconnect lines 13 make up the network of electricalconnections that are created throughout layers 14. Overlying and on thesurface of layers 14 are points 16 of electrical contact. These points16 of electrical contact can for instance be bond pads that establishthe electrical interconnects to the transistors and other devices thathave been provided in the surface of the substrate 10. These points ofcontact 16 are points of interconnect within the IC arrangement thatneed to be further connected to surrounding circuitry. The conductiveinterconnect lines 13 or contact points 16 or conductive vias makingcontact with at least one of said points of electrical contact providedto said semiconductor devices in or on the surface of said substrate 10.These points 16 of electrical contact having been provided in or on thesurface of said overlaying interconnecting metalization structure 14comprise a material that is selected from a group comprising sputteredaluminum, CVD tungsten, CVD copper, electroplated gold, electroplatedsilver, electroplated copper, electroless gold and electroless nickel. Apassivation layer 18, formed of for example silicon nitride, isdeposited over the surface of layers 14 to protect underlying layersfrom moisture, contamination, etc.

The key steps of the above referenced application begin with thedeposition of a thick layer 20 of polyimide that is deposited over thesurface of layer 18. Access must be provided to points of electricalcontact 16, for this reason a pattern of openings 22, 36 and 38 isetched through the polyimide layer 20 and the passivation layer 18, thepattern of openings 22, 36 and 38 aligns with the pattern of electricalcontact points 16. Contact points 16 are, by means of the openings22/36/38 that are created in the layer 20 of polyimide, electricallyextended to the surface of layer 20.

The above referenced material that is used for the deposition of layer20 is polyimide, the material that can be used for this layer is notlimited to polyimide but can contain any of the known polymers(SiCl_(x)O_(y)). The indicated polyimide is the preferred material to beused for the processes of the invention for the thick layer 20 ofpolymer. Examples of polymers that can be used are silicons, carbons,fluoride, chlorides, oxygens, parylene or teflon, polycarbonate (PC),polysterene (PS), polyoxide (PO), poly polooxide (PPO), benzocyclobutene(BCB).

Electrical contact with the contact points 16 can now be established byfilling the openings 22/36/38 with a conductive material. The topsurfaces 24 of these metal conductors that are contained in openings22/36/38 can now be used for connection of the IC to its environment,and for further integration into the surrounding electrical circuitry.This latter statement is the same as saying that semiconductor devicesthat have been provided in the surface of substrate 10 can, via theconductive interconnects contained in openings 22/36/38, be furtherconnected to surrounding components and circuitry. Interconnect pads 26and 28 are formed on top of surfaces 24 of the metal interconnectscontained in openings 22, 36 and 38. These pads 26 and 28 can be of anydesign in width and thickness to accommodate specific circuit designrequirements. A pad can, for instance, be used as a flip chip pad. Otherpads can be used for power distribution or as a ground or signal bus.The following connections can, for instance, be made to the pads shownin FIG. 1: pad 26 can serve as a flip chip pad, pad 28 can serve as aflip chip pad or can be connected to electrical power or to electricalground or to an electrical signal bus. There is no relation between thesize of the pads shown in FIG. 1 and the suggested possible electricalconnections for which this pad can be used. Pad size and the standardrules and restrictions of electrical circuit design determine theelectrical connections to which a given pad lends itself.

The following comments relate to the size and the number of the contactpoints 16, FIG. 1. Because these contact points 16 are located on top ofa thin dielectric (layers 14, FIG. 1) the pad size cannot be too largesince a large pad size brings with it a large capacitance. In addition,a large pad size will interfere with the routing capability of thatlayer of metal. It is therefore preferred to keep the size of the pad 16relatively small. The size of pad 16 is however also directly relatedwith the aspect ratio of vias 22/36/38. An aspect ratio of about 5 isacceptable for the consideration of via etching and via filling. Basedon these considerations, the size of the contact pad 16 can be in theorder of 0.5 μm to 30 μm, the exact size being dependent on thethickness of layers 18 and 20.

There is not imposed any limitation on the number of contact pads thatcan be included in the design, this number is dependent on packagedesign requirements. Layer 18 in FIG. 1 can be a typical IC passivationlayer.

The most frequently used passivation layer in the present state of theart is plasma enhanced CVD (PECVD) oxide and nitride. In creating layer18 of passivation, a layer of approximately 0.2 μm PECVD oxide can bedeposited first followed by a layer of approximately 0.7 μm nitride.Passivation layer 18 is very important because it protects the devicewafer from moisture and foreign ion contamination. The positioning ofthis layer between the sub-micron process (of the integrated circuit)and the tens-micron process (of the interconnecting metalizationstructure) is of critical importance since it allows for a cheaperprocess that possibly has less stringent clean room requirements for theprocess of creating the interconnecting metalization structure.

Layer 20 is a thick polymer dielectric layer (for example polyimide)that have a thickness in excess of 2 μm (after curing). The range of thepolymer thickness can vary from 2 μm to 150 μm, dependent on electricaldesign requirements.

For the deposition of layer 20 the Hitachi-Dupont polyimide HD 2732 or2734 can, for example, be used. The polyimide can be spin-on coated andcured. After spin-on coating, the polyimide will be cured at 400 degreesC. for about 1 hour in a vacuum or nitrogen ambient. For a thicker layerof polyimide, the polyimide film can be multiple coated and cured.

Another material that can be used to create layer 20 is the polymerbenzocyclobutene (BCB). This polymer is at this time commerciallyproduced by for instance Dow Chemical and has recently gained acceptanceto be used instead of typical polyimide application.

The dimensions of openings 22, 36 and 38 have previously been discussed.The dimension of the openings together with the dielectric thicknessdetermine the aspect ratio of the opening. The aspect ratio challengesthe via etch process and the metal filling capability. This leads to adiameter for openings 22/36/38 in the range of approximately 0.5 μm to30 μm, the height for openings 22/36/38 can be in the range ofapproximately 2 μm to 150 μm. The aspect ratio of openings 22/36/38 isdesigned such that filling of the via with metal can be accomplished.The via can be filled with CVD metal such as CVD tungsten or CVD copper,with electro-less nickel, with a damascene metal filling process, withelectroplating copper, etc.

Extensions can be provided by applying multiple layers of polymer (suchas polyimide) and can therefore be adapted to a larger variety ofapplications. The function of the structure that has been described inFIG. 1 can be further extended by depositing a second layer of polyimideon top of the previously deposited layer 20 and overlaying the pads 26and 28. Selective etching and metal deposition can further createadditional contact points on the surface of the second layer ofpolyimide that can be interconnected with pads 26 and 28. Additionallayers of polyimide and the thereon created contact pads can becustomized to a particular application, the indicated extension ofmultiple layers of polyimides greatly enhances the flexibility andusefulness of the invention.

FIG. 1 shows a basic design advantage which allows for submicron orfine-lines, that run in the immediate vicinity of the metal layers 14and the contact points 16, to be extended in an upward direction 30through metal interconnect 36. This extension continues in the direction32 in the horizontal plane of the metal interconnect 28 and comes backdown in the downward direction 34 through metal interconnect 38. Thefunctions and constructs of the passivation layer 18 and the insulatinglayer 20 remain as previously highlighted. This basic design advantageof the invention is to “elevate” or “fan-out” the fine-lineinterconnects and to remove these interconnects from the micro andsub-micro level to a metal interconnect level that has considerablylarger dimensions and that therefore has smaller resistance andcapacitance and is easier and more cost effective to manufacture. Thisdoes not include any aspect of conducting line re-distribution andtherefore has an inherent quality of simplicity. It therefore furtheradds to the importance of the referenced application in that it makesmicro and sub-micro wiring accessible at a wide and thick metal level.The interconnections 28, 36 and 38 interconnect the fine-level metal bygoing up through the passivation and polymer or polyimide dielectriclayers, continuing over a distance on the wide and thick metal level andcontinuing by descending from the wide and thick metal level back downto the fine-metal level by again passing down through the passivationand polymer or polyimide dielectric layers. The extensions that are inthis manner accomplished need not be limited to extending fine-metalinterconnect points 16 of any particular type, such as signal or poweror ground, with wide and thick metal line 26 and 28. The laws of physicsand electronics will impose limitations, if any, as to what type ofinterconnect can by established in this manner, limiting factors will bethe conventional electrical limiting factors of resistance, propagationdelay, RC constants and others. Where the referenced application is ofimportance is that the referenced continuation-in-part applicationprovides much broader latitude in being able to apply these laws and, inso doing, provides a considerably extended scope of the application anduse of Integrated Circuits and the adaptation of these circuits to awide and thick metal environment.

FIG. 2 shows how the basic interconnect aspect can further be extendedunder the present invention to not only elevate the fine-metal to theplane of the wide and thick metal but to also add an inductor on thesurface of the thick layer 20 of polyimide. The inductor is created in aplane that is parallel with the surface of the substrate 10 whereby thisplane however is separated from the surface of the substrate 10 by thecombined heights of layers 12, 14, 18, and 20. FIG. 2 shows a crosssection 40 of the inductor taken in a plane that is perpendicular to thesurface of substrate 10. The wide and thick metal will also contributeto a reduction of the resistive energy losses. Furthermore, the lowresistivity metal, such as gold, silver and copper, can be applied usingelectroplating, the thickness can be about 20 μm.

FIG. 3 shows a top view 42 of the spiral structure of the inductor 40that has been created on the surface of layer 20 of dielectric. Thecross section that is shown in FIG. 2 of the inductor 40 has been takenalong the line 2-2′ of FIG. 3. The method used for the creation of theinductor 40 uses conventional methods of metal, such as gold, copper andthe like, deposition by electroplating or metal sputter processes.

FIG. 4 shows a top view of inductor 40 whereby the inductor has beenfurther isolated from the surface of the substrate 10 by the addition oflayer 44 of ferromagnetic material. The layer 44 has a thickness ofbetween about 1,000 and 50,000 Angstrom. Openings are created in layer44 of ferromagnetic material for the conductors 36 and 38, the layer 44is deposited using conventional methods to a thickness that can beexperimentally determined and that is influenced by and partiallydependent on the types of materials used and the thickness of the layersthat are used overlying the ferromagnetic material (such as layer 20)for the creation of the structure that is shown in cross section in FIG.4. The surface area of the ferromagnetic layer 44 typically extends overthe surface of layer 18 such that the inductor 40 aligns with andoverlays the layer 44, the surface area of layer 44 can be extendedslightly beyond these boundaries to further improve shielding thesurface of substrate 10 from the electromagnetic field of inductor 40.

Layer 44 is not limited to being a layer of ferromagnetic material butcan also be a layer of a good conductor such as but not limited to gold,copper and aluminum. The overlying inductor 40 that is created on thesurface of layer 20 of polyimide can be isolated from the underlyingsilicon substrate 10 by a layer 44 that comprises either ferromagneticor a good conductor.

FIG. 5 a shows, for reasons of clarity, a simplified cross section ofthe substrate and the layers that are created on the surface of thesubstrate under the processes of the invention, the highlighted areasthat are shown have previously been identified as:

-   -   10, the silicon substrate    -   12, a layer of dielectric that has been deposited over the        surface of the substrate    -   14, an interconnect layer that contains interconnect lines, vias        and contact points    -   16, contact points on the surface of the interconnect layer 14    -   18, a layer of passivation into which openings have been created        through which the contact points 16 can be accessed    -   20, a thick layer of polymer, and    -   21, conductive plugs that have been provided through the layer        20 of polyimide.

The thick layer 20 of polymer can be coated in liquid form on thesurface of the layer 18 of passivation or can be laminated over thesurface of layer 18 of passivation by dry film application. Vias thatare required for the creation of conductive plugs 21 can be defined byconventional processes of photolithography or can be created using laser(drill) technology.

It is clear from previous discussions that the sequence of layers thatis shown in cross section in FIG. 5 a has been created so thatadditional electrical components such as an inductor, a capacitor andthe like can be created on the surface of layer 20 of polyimide and inelectrical contact with conductive plugs 21. Layer 12 of dielectric may,in the cross section that is shown in FIG. 5 a, be part of layer 14since layer 14 is a layer of Intra Level Dielectric (ILD) within whichlayer 12 can be readily integrated.

With respect to the cross section that is shown in FIG. 5 b, the samelayers that have been identified for FIG. 5 a are again provided in thiscross section. Additionally has been shown the upper layer 17 of thesilicon substrate 10 that contains active semiconductor devices. Alsoshown is the cross section of an inductor 19 that has been created onthe surface of layer 18 of passivation. It must again be emphasized thatthe ohmic resistivity of the metal that is used for inductor 19 must beas low as possible. For this reason, the use of a thick layer of forinstance gold is preferred for the formation of inductor 19. It has beenshown that a thick layer of gold increased the Q value of inductor 19from about 5 to about 20 for 2.4 GHz applications, which represents asignificant improvement in the Q value of inductor 19.

FIG. 6 a shows a cross section of a capacitor that has been created onthe surface of a substrate 10. A layer 14 of conductive interconnectlines and contact points has been created on the surface of substrate10. A layer 18 of passivation has been deposited over the surface oflayer 14, openings have been created in layer 18 of passivation throughwhich the surface of contact pads 16 can be accessed.

A capacitor contains, as is well known, a lower plate, an upper plateand a layer of dielectric that separates the upper plate from the lowerplate. These components of a capacitor can be readily identified fromthe cross section that is shown in FIG. 6 a, as follows:

-   -   42 is a conductive layer that forms the lower plate of the        capacitor    -   44 is a conductive layer that forms the upper plate of the        capacitor    -   46 is the dielectric layer that separates the upper plate 44 of        the capacitor from the lower plate 42.

It must be noted from the cross section that is shown in FIG. 6 a thatthe capacitor has been created on the surface of layer 18 ofpassivation, the process of creating the capacitor is therefore referredto as a post-passivation processing sequence. Processing conditions andmaterials that can be used for the creation of the respective layers 42,44 and 46 have already been highlighted and need therefore not befurther detailed at this time.

The main points of interest are the various thicknesses to which thethree layers 42, 44 and 46 can be deposited, as follows:

-   -   layer 18 of passivation between about 0.1 μm and 0.3 μm    -   layer 42 of conductive material between about 0.5 and 20 μm    -   layer 46 of dielectric between about 500 and 10,000 Angstrom,        and    -   layer 44 of conductive material between about 0.5 and 20 μm.

The post-passivation created capacitor that is shown in cross section inFIG. 6 a has:

-   -   reduced parasitic capacitance between the capacitor and the        underlying silicon substrate    -   allowed for the use of a thick layer of conductive material,        reducing the resistance of the capacitor; this is particularly        important for wireless applications    -   allowed for the use of high-dielectric material such as TiO₂,        Ta₂O₅ for the dielectric between the upper and the lower plate        of the capacitor, resulting in a higher capacitive value of the        capacitor.

FIG. 6 b shows a three-dimensional view of the solenoid structure of aninductor 19 that has been created on the surface of the layer 18 ofpassivation. Further highlighted in FIG. 6 b are:

-   -   23, vias that are created in the thick layer of polymer 20, FIG.        5 a, for the interconnects of the upper and the lower levels of        metal of the inductor    -   25, the bottom metal of the inductor    -   27, the top metal for the inductor.

FIG. 6 c shows a three dimensional view of an inductor that has beencreated on the surface of a layer 18 of passivation by first depositinga thick layer 29 of polymer over which a layer (not shown) of polymer isdeposited, vias 23 are created in the thick layer 20 (FIG. 5 a) ofpolymer. In addition to the previously highlighted layers, FIG. 6 cshows a layer 29 of polyimide. The inductor 19 is created by creatingthe bottom metal 25 of the inductor 19, the top metal 27 of the inductorand the vias 23 that are created in layer 20 (FIG. 5 a) that preferablycontains a polymer.

FIG. 6 d shows a top view of layer 20 on the surface of which aninductor has been created as previously shown in FIG. 6 c. Vias 23 arehighlighted as are top metal lines 27 of the inductor 19, bottom metallines 25 of the inductor 19 (hatched since they are not visible on thesurface of the layer 20). Further detailed are vias 23′ and 23″, thelower extremity of via 23′ and the upper extremity of via 23″ areconnected to interconnect lines 31 and 33 (FIG. 6 e) respectively,theses interconnect lines 31 and 33 provide the connection for furtherinterconnect of the inductor 19.

FIG. 6 e shows a cross section of the structure of FIG. 6 d whereby thiscross section is taken along the line 6 e-6 e′ that is shown in FIG. 6d. Contact pads 16′ have been provided on the surface of layer 18 ofpassivation, these contact pads 16′ make contact with the vias 23, 23′and 23″ for interconnection between the bottom metal 25 of inductor 19and the upper metal 27 of the inductor 19. Interconnects to vias 23′ and23″ are the lines 31 and 33 which, as previously stated, connect theinductor 19 to surrounding electrical circuitry or components.

The creation of a toroidal inductor overlying a layer of passivation hasbeen shown in FIGS. 6 f and 6 g where toroidal coil 19′ is created onthe surface of a layer 18 of passivation. Top level metal 27′, bottomlevel metal 25′ and vias 23′ that interconnect bottom level metal 25′with top level metal 27′ have been highlighted in FIG. 6 f.

FIG. 6 g shows, for further clarification, a top view of the toroidal19′ of FIG. 6 f. The highlighted features of this figure have previouslybeen explained and therefore do not need to be further discussed at thistime.

FIG. 7 shows a cross section where, as in FIG. 6 a, a capacitor iscreated on the surface of substrate 10. In the cross section that isshown in FIG. 7 however a thick layer 20 of polyimide has been depositedover the surface of the passivation layer 18 and has been patterned andetched in order to make the contact pads 16 accessible though the thicklayer 20 of poly. The thick layer 20 of polymer removes most of thecapacitor, that is the lower plate 42, the upper plate 44 and thedielectric 46, from the surface of substrate 10 by a distance that isequal to the thickness of layer 20. It has previously been state thatthe range of polyimide thickness can vary from 2 μm to 150 μm and isdependent on electrical design requirements. This statement is alsovalid for the cross section shown in FIG. 7, the layers of the capacitorcan therefore be removed from the surface of substrate 10 by a distanceof 2 μm to 150 μm. It is clear that this leads to a significant increasein distance between the capacitor and the underlying silicon substrate,the parasitic capacitance will therefore be significantly reduced.

FIG. 8 shows a cross section of a substrate 10 on the surface of whichhas been deposited a layer 18 of passivation, a resistor 48 has beencreated on the surface of the layer 18 of passivation. A resistor, as iswell known, is created by connecting two points with a material thatoffers electrical resistance to the passage of current through thematerial. The two points that are part of the resistance 48 that isshown in cross section in FIG. 8 are the contact pads 16 that have beencreated in or on the surface of the interconnect layer 14. By creatinglayer 48 between the two contact pads, that interconnects the twocontact pads and that is deposited on the surface of passivation layer18, a resistor has been created in accordance with the processes of theinvention. For the creation of layer 48 a high resistivity material canbe used such as TaN, silicon nitride, phosphosilicate glass (PSG),silicon oxynitride, aluminum, aluminum oxide (Al_(x)O_(y)), tantalum,nionbium, or molybdenum. It is clear that dimensions such as thickness,length and width of deposition of layer 48 of high resistivity materialare application dependent and can therefore not be specified at thistime in any detail. The resistor that is shown in cross section in FIG.8 is, as are the capacitors of FIGS. 6 a and 7, created in apost-passivation process on the surface of layer 18 of passivation.

FIG. 9 shows a cross section of a substrate 10, an interconnect layer 14has been created on the surface of the substrate. A layer 18 ofpassivation has been deposited over the layer 14 of interconnect metal,a thick layer 20 of polyimide has been deposited over the surface of thepassivation layer 18. A resistor 48 has been created on the surface ofthe layer 20 of polyimide. The resistor 48 is created connecting the twocontact pads 16 with a thin high resistivity layer of metal. Byincreasing the distance between the body of the resistor and the surfaceof substrate (by the thickness of the poly layer 20) the parasiticcapacitance between the body of the resistor and the substrate isreduced resulting in an improved resistive component (reduced parasiticcapacitive loss, improved high frequency performance).

Further applications of the post-passivation processing of the inventionare shown in FIGS. 10 and 11, which concentrate on making ball contactpoints between contact pads 16 and an overlying electric component, suchas a discrete inductor. Proceeding from the surface of substrate 10 inan upward direction, most of the layers that are shown in FIG. 10 havepreviously been identified and are identified in FIG. 10 using the samenumerals as have previously been used for these layers. Where FIG. 10shows previously not identified layers is in:

-   -   50, contact plugs that have been formed through the thick layer        20 of polymer    -   52, contact balls that have been formed on the surface of the        contact plugs 50 using conventional methods of selective solder        deposition, the solder ball is created by electroplating, screen        printing, and ball mounting, the application of a flux on the        deposited solder and flowing the solder to form the contact        balls 52, and    -   54, a cross section of a discrete electrical component such as        an inductor or a discrete capacitor or a resistor.

FIG. 11 shows a cross section of a silicon substrate 10 on the surfaceof which a discrete electrical component 54 has been mounted, contactballs 56 are used whereby the distance between the substrate 10 and theelectrical component 54 is of a significant value. Contact balls areinserted into the openings that have been created in the layer 18 ofpassivation overlying the contact pads 16, the (relatively large)contact balls 56 create a significant separation between the surface ofsubstrate 10 and the discrete electrical component 54.

The methods that have been shown in FIGS. 10 and 11 indicate that:

-   -   the passive component 54 is removed from the surface of        substrate 10 by a significant distance, and    -   instead of mounting the passive, discrete component 54 on the        surface of a Printed Circuit Board (PCB), the passive component        54 can be mounted closer to a semiconductor device in the        present invention.

Throughout the methods and procedures that have been explained aboveusing the examples that are shown in cross section in the accompanyingdrawings, the following has been adhered to:

-   -   the passive components have been further removed from the        silicon substrate, thereby reducing the negative impact that is        induced by the substrate due to electromagnetic losses incurred        in the substrate the post-passivation process of the invention        allows for the selection of discrete component design parameters        that result in reduced resistance of the discrete capacitor and        the discrete inductor, this is further clear from the following        comparison between prior art processes and the processes of the        invention.

Prior art requires for the creation of an inductor:

-   -   the use of thin metal, which imposes the creation of    -   wide coils for an inductor resulting in    -   increased surface area that is required for the inductor which        in turn increases the parasitic capacitance of the inductor        causing eddy current losses in the surface of the substrate.

The present invention by contrast:

-   -   can use thick metal, since the metal of the passive component is        (by the thick layer of polymer) removed from the (thin metal)        interconnect layer 14, and (as a consequence)    -   reduces the surface area that is required for the inductor, and

reduces the resistivity of the inductor, thereby increasing the Q valueof the inductor.

Although the preferred embodiment of the present invention has beenillustrated, and that form has been described in detail, it will bereadily understood by those skilled in the art that variousmodifications may be made therein without departing from the spirit ofthe invention or from the scope of the appended claims.

1. An integrated circuit chip comprising: a silicon substrate; multiplesemiconductor devices in or on said silicon substrate, wherein one ofsaid multiple semiconductor devices comprises a transistor; a firstdielectric layer over said silicon substrate; a metallization structureover said first dielectric layer, wherein said metallization structureis connected to said multiple semiconductor devices, wherein saidmetallization structure comprises a first metal layer and a second metallayer over said first metal layer, and wherein said metallizationstructure comprises electroplated copper; a second dielectric layerbetween said first and second metal layers; a passivation layer oversaid metallization structure and over said first and second dielectriclayers, wherein said passivation layer comprises a topmost oxide layerof said integrated circuit chip and a topmost nitride layer of saidintegrated circuit chip, wherein said topmost nitride layer is over saidtopmost oxide layer; a first polymer layer over said passivation layer,wherein said first polymer layer has a thickness between 2 and 150micrometers and greater than those of said passivation layer and saidfirst and second dielectric layers; a coil on said first polymer layer,wherein said coil comprises an electroplated metal layer, and whereinsaid coil has a thickness greater than those of said first and secondmetal layers; a metal line on said first polymer layer, wherein saidmetal line has a thickness greater than those of said first and secondmetal layers, wherein said metal line and said coil are separate fromeach other; and a second polymer layer over said metal line.
 2. Theintegrated circuit chip of claim 1, wherein said coil comprises gold. 3.The integrated circuit chip of claim 1, wherein said coil comprisescopper.
 4. The integrated circuit chip of claim 1, wherein said firstpolymer layer comprises polyimide.
 5. The integrated circuit chip ofclaim 1, wherein said first polymer layer comprises benzocyclobutene(BCB).
 6. The integrated circuit chip of claim 1, wherein said topmostnitride layer has a thickness greater than that of said topmost oxidelayer.
 7. The integrated circuit chip of claim 1 further comprising athird metal layer between said coil and said passivation layer, whereinsaid third metal layer has a thickness between 0.2 and 5 micrometers. 8.An integrated circuit chip comprising: a silicon substrate; multiplesemiconductor devices in or on said silicon substrate, wherein one ofsaid multiple semiconductor devices comprises a transistor; a firstdielectric layer over said silicon substrate; a metallization structureover said first dielectric layer, wherein said metallization structureis connected to said multiple semiconductor devices, wherein saidmetallization structure comprises a first metal layer and a second metallayer over said first metal layer, and wherein said metallizationstructure comprises electroplated copper; a second dielectric layerbetween said first and second metal layers; a passivation layer oversaid metallization structure and over said first and second dielectriclayers, a first passivation opening in said passivation layer exposing afirst pad of said metallization structure, and a second passivationopening in said passivation layer exposing a second pad of saidmetallization structure, wherein said first and second pads are separatefrom each other, wherein said passivation layer comprises a topmostoxide layer of said integrated circuit chip and a topmost nitride layerof said integrated circuit chip, wherein said topmost nitride layer isover said topmost oxide layer; a first polymer layer over saidpassivation layer, a first polymer opening in said first polymer layerexposing said first pad, and a second polymer opening in said firstpolymer layer exposing said second pad, wherein said first polymer layerhas a thickness between 2 and 150 micrometers and greater than those ofsaid passivation layer and said first and second dielectric layers; acoil over said first polymer layer, wherein said coil is connected tosaid first pad through said first polymer opening and said firstpassivation opening, wherein said coil comprises electroplated copper,and wherein said coil has a thickness greater than those of said firstand second metal layers; a metal line on said first polymer layer,wherein said metal line is connected to said second pad through saidsecond polymer opening and said second passivation opening, and whereinsaid metal line has a thickness greater than those of said first andsecond metal layers, and wherein said metal line and said coil areseparate from each other; and a second polymer layer over said metalline.
 9. The integrated circuit chip of claim 8, wherein said firstpolymer layer comprises polyimide.
 10. The integrated circuit chip ofclaim 8, wherein said first polymer layer comprises benzocyclobutene(BCB).
 11. The integrated circuit chip of claim 8, wherein said topmostnitride layer has a thickness greater than that of said topmost oxidelayer.
 12. The integrated circuit chip of claim 8 further comprising athird metal layer between said coil and said passivation layer, whereinsaid third metal layer has a thickness between 0.2 and 5 micrometers.13. The integrated circuit chip of claim 8, wherein said firstpassivation opening has a transverse dimension between 0.5 and 30micrometers.
 14. The integrated circuit chip of claim 8, wherein saidmetal line comprises a power connection.
 15. The integrated circuit chipof claim 8, wherein said metal line comprises a ground connection. 16.The integrated circuit chip of claim 8, wherein said metal linecomprises a signal connection.
 17. An integrated circuit chipcomprising: a silicon substrate; multiple semiconductor devices in or onsaid silicon substrate, wherein one of said multiple semiconductordevices comprises a transistor; a first dielectric layer over saidsilicon substrate; a metallization structure over said first dielectriclayer, wherein said metallization structure is connected to saidmultiple semiconductor devices, wherein said metallization structurecomprises a first metal layer and a second metal layer over said firstmetal layer, and wherein said metallization structure compriseselectroplated copper; a second dielectric layer between said first andsecond metal layers; a passivation layer over said metallizationstructure and over said first and second dielectric layers, wherein saidpassivation layer comprises a topmost oxide layer of said integratedcircuit chip and a topmost nitride layer of said integrated circuitchip, wherein said topmost nitride layer is over said topmost oxidelayer; a first polymer layer over said passivation layer, wherein saidfirst polymer layer has a thickness between 2 and 150 micrometers andgreater than those of said passivation layer and said first and seconddielectric layers; a coil on said first polymer layer, wherein said coilcomprises a gold layer, and wherein said coil has a thickness greaterthan those of said first and second metal layers; a metal line on saidfirst polymer layer, wherein said metal line has a thickness greaterthan those of said first and second metal layers, and wherein said metalline and said coil are separate from each other; and a second polymerlayer over said metal line.
 18. The integrated circuit chip of claim 17,wherein said first polymer layer comprises polyimide.
 19. The integratedcircuit chip of claim 17, wherein said first polymer layer comprisesbenzocyclobutene (BCB).
 20. The integrated circuit chip of claim 17,wherein said topmost nitride layer has a thickness greater than that ofsaid topmost oxide layer.
 21. The integrated circuit chip of claim 17further comprising a third metal layer between said coil and saidpassivation layer, wherein said third metal layer has a thicknessbetween 0.2 and 5 micrometers.
 22. The integrated circuit chip of claim17, wherein said first passivation opening has a transverse dimensionbetween 0.5 and 30 micrometers.
 23. The integrated circuit chip of claim17, wherein said gold layer comprises an electroplated gold.
 24. Theintegrated circuit chip of claim 17, wherein said gold layer comprises asputtered gold.
 25. The integrated circuit chip of claim 17, whereinsaid metal line comprises a power connection, a ground connection or asignal connection.